This invention relates to a semiconductor device comprising an MOS (metal oxide semiconductor) transistor of a first channel type formed on a semiconductor substrate, and an MOS transistor of a second channel type formed on said first MOS transistor with a common gate electrode interposed therebetween.
FIG. 1 represents a conventional inverter circuit comprised of complementary channel type MOS transistors. Referring to the circuit diagram of FIG. 1, the P channel MOS transistor 1 and N channel MOS transistor 2 are connected in series between the power source voltage V.sub.DD and a ground. The gates of the MOS transistors 1 and 2 are jointly connected to an input terminal INPUT. The drains of the MOS transistors 1 and 2 are connected together and their junction constitutes the output terminal of the inverter circuit, and is connected to an output terminal OUTPUT. FIG. 2 is a sectional view of the inverter circuit of FIG. 1. Referring to FIG. 2, an N.sup.+ drain region 12 and N.sup.+ source region 13 are formed in a P conductivity substrate 11 with a certain space allowed therebetween. An SiO.sub.2 film 15 is deposted on the substrate r11 involving the above-mentioned N.sup.+ drain and source regions 12 and 13. Formed on that portion of an SiO.sub.2 film 15 which faces the interventing space between the aforesaid N.sup.+ regions 12 and 13 (the channel region) is a gate electrode 14 composed of an N.sup.+ polysilicon layer.
An N channel MOS transistor is constituted by N.sup.+ regions 12 and 13, a chanel region provided in that portion of the substrate 11 which lies between said N.sup.+ regions 12 and 13, an SiO.sub.2 film 15, and an N.sup.+ polysilicon film which is provided as a gate electrode 14. An SiO.sub.2 film 19 is deposited on the N.sup.+ polysilicon gate electrode 14. An N.sup.+ channel region 18 is laid on that region of the SiO.sub.2 film 19 which faces the polysilicon gate electrode 14. A P.sup.+ semiconductor drain region 16 is provided on the SiO.sub.2 films 15 and 19. A PN junction is provided between the P.sup.+ drain region 16 and N.sup.+ channel region 18. The P.sup.+ drain region 16 lies above the N.sup.+ region 12. A P.sup.+ semiconductor source region 17 is deposited on the SiO.sup.2 films 15 and 19. A PN junction is provided between the P.sup.+ source region 17 and N.sup.+ channel region 18. The P.sup.+ source region 17 lies above the N.sup.+ region 13. The above-mentioned P.sup.+ regions 16 and 17, N.sup.+ region 18, N.sup.+ polysilicon gate electrode 14 and SiO.sub.2 film 15 jointly constitute the P channel MOS transistor. The drain region 12 of the N channel MOS transistor and the drain region 16 of the P channel MOS transistor are electrically connected by means of an N.sup.+ polysilicon layer 20 and aluminum layer 21. Reference numeral 22 represents an SiO.sub.2 film, and reference numeral 23 denotes a PSG film acting as a passivation film.
In the above-mentioned conventional inverter circuit of FIG. 2, the drain region 12 of the N channel MOS transistor mounted on the silicon substrate 11, and the drain region 16 of the P channel MOS transistor deposted on said N channel MOS transistor are connected by an aluminum layer 21 to effect ohmic contact between both drain regions 12 and 16. If the N.sup.+ type drain region 12 is made to contact the P.sup.+ type drain region 16 directly, a PN junction is formed on said contact plane. In this case, a potential barrier of a certain magnitude is generated at the PN junction, making it impossible to establish ohmic contact between both drain regions 12 and 16. The aluminium layer 21 ensures ohmic contact between the N.sup.+ drain region 12 and P.sup.+ drain region 16. In the conventional inverter circuit, the drain regions 12 and 16 contact the aluminium layer 21 lengthwise along the surface of the inverter circuit in such a manner that the contact planes do not overlap each other. Therefore, a large area has to be provided on the substrate to allow for contact between the aluminium layer 21 and drain regions 12 and 16, thereby limiting the degree to which integration of the conventional inverter circuit can be improved.
FIG. 3 shows the pattern of a memory cell involving the conventional inverter circuit. FIG. 4 indicates the schematic circuit diagram of said memory cell. Reference numerals B, B denote bit lines, and W represents a word line. Reference numeral 31 (FIG. 3) shows an N.sup.+ diffusion region formed in the P semiconductor substrate. Reference numerals 32 and 33 denote aluminium layers for effecting connection between the drain regions of complementary channel type MOS transistors. Reference numerals 34 to 37 (FIG. 4) indicate MOS transistors jointly constituting a flip-flop circuit. Reference numerals 38 and 39 show MOS transistors acting as transfer elements. As seen from FIG. 3, the memory cell arranged as described above causes the aluminium layers to contact the drain regions over a consideraly large area.